A 10.7 MHz CMOS SC radio IF filter using orthogonal hardware modulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm2 in a 0.6 µm CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filter

Integrated test support features for multi-GHz DACs in 28nm CMOS

This paper presents a 7GSps 6b current-steering DAC in 28nm CMOS for VLSI SoC embedding which includes on-chip memory and clock generation circuits for wafer-sort testing. Several linearization techniques are implemented to extend linearity to very high frequencies with levels of SFDR>50dB for signals up to 1GHz, while keeping the DAC footprint small - 0.035mm². Testing at full speed is facilitated by means of integrating a digital front-end BIST scheme in 0.048mm². It uses a 5kbit 8X TI data memory, based on circular shift registers to avoid signal-dependent disturbances. An integrated 7 GHz CML ring oscillator type clock generator, as well as a serial data interface, simplify and reduce the cost of testing the DAC at high-speed

A novel temperature and disturbance insensitive DAC calibration method

This paper presents a new foreground DAC calibration method that is insensitive to temperature fluctuations and on-chip disturbances. In the proposed current cell, the same number of unit transistors is always used, guaranteeing matched response for all current cells. These transistors are divided in two groups: a fixed group and a configurable group. The unit transistors in the configurable group can be interchanged with additional redundant unit transistors, such that the mismatch errors of the configurable group compensate the mismatch errors of the fixed group. Together they generate the needed output current. Thus all current cells feature matched temperature coefficients and dynamic response. For an exemplary 6+6bits segmented current steering DAC, the expected 99% yield INL improves with almost 3 bits while using only 30% additional unit transistors

A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with data-driven noise reduction

Low-power sensor applications e.g. for environmental monitoring, bio-potential recording, and wireless autonomous sensor networks require highly power-efficient ADCs, typically with resolutions of at least 10b. SAR ADCs are generally beneficial in terms of power efficiency. However, the most power-efficient designs currently lack the required accuracy for these applications [1, 2], as they are limited to 9b ENOB. Other designs that have sufficient accuracy (10b) are limited to power efficiencies above 10fJ/conv-step [3]. The aim of this work is to increase the accuracy of highly efficient SAR ADCs beyond 10b, while further improving the efficiency to 2.2fJ/conv-step. To do so, this work introduces a Data-Driven Noise-Reduction method to efficiently suppress comparator noise, applies a segmented capacitive DAC with 250aF unit elements for better efficiency and accuracy, and implements a self-oscillating comparator to locally generate the internally required oversampled clock

Sigma-Delta Modulators Operating at a Limit Cycle

A new type of sigma–delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital–analog converter waveform asymmetry and a higher tolerance to clock imperfections The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs

Receiver front ends with robustness to process variations

Not available

A 9.8-11.5-GHz Quadrature ring oscillator for optical receivers

This paper describes a quadrature ring oscillator that is tunable from 9.8 to 11.5 GHz in a 30-GHz fT BiCMOS technology. The ring oscillator can be used in advanced data clock recovery architectures in optical receivers. The circuit implementation of the oscillator uses transistors as active inductances. Isolation between the oscillator and cascaded circuits, such as buffers and flip-flops, is improved by utilizing the active inductances in a cascode configuration. Carrier to noise ratios better than 94 dBc/Hz at 2-MHz offset are measured with 75-mW dissipation and 2.7-V supply voltage. The evolution in two-stage ring oscillator topologies, leading to the realized design, is discussed in detail on the circuit leve

Mismatch-Based Timing Errors in Current Steering DACs

Current Steering Digital-to-Analog Converters (CS-DAC) are important ingredients in many high-speed data converters. Various types of timing errors such as mismatch based timing errors limit broad-band performance. A framework of timing errors is presented here and it is used to analyze these errors. The extracted relationship between performance, block requirements and architecture (e.g segmentation) gives insight on design tradeoffs in Nyquist DACs and multi-bit current-based /spl Sigma//spl Delta/ Modulators